1. Field of the Invention
The invention relates to a semiconductor memory apparatus, and more particularly to a semiconductor memory apparatus that reads data of a (NAND) flash memory in a current sensing manner, and a method for erasing the semiconductor memory apparatus.
2. Description of Related Art
FIG. 1 illustrates an example of a bit line selection circuit and a page buffer/sensing circuit of a conventional flash memory, in which a pair of bit lines including an even bit line GBL_e and an odd bit line GBL_o is exemplarily illustrated. The bit line selection circuit 10 includes an even select transistor SEL_e electrically connected with the even bit line GBL_e and an odd select transistor SEL_o electrically connected with the odd bit line GBL_o, an even bias select transistor YSEL_e electrically connected between the even bit line GBL_e and a virtual potential VIR, an odd bias select transistor YSEL_o electrically connected between the odd bit line GBL_o and the virtual potential VIR, and a bit line select transistor BLS electrically connected with a common node N1 which is electrically connected with the even select transistor SEL_e and the odd select transistor SEL_o.
Each of the even bit line GBL_e and the odd bit line GBL_o is electrically connected with a NAND string NU. Each NAND string NU includes a plurality of memory cells connected in series along the column direction and a drain select transistor and a source select transistor electrically connected with two ends thereto. The drain select transistor is electrically connected with the even bit line GBL_e or the odd bit line GBL_o, and the source select transistor is electrically connected with a common source line SL.
A sensing circuit 20 has a pre-charge transistor BLPRE for providing a pre-charge potential to each bit line, a capacitor C electrically connected with a sense node SN formed between the pre-charge transistor BLPRE and the bit line select transistor BLS, and a transfer transistor BLCD transferring the potential of the sense node SN to a latch circuit 22.
When the even bit line GBL_e is selected but the odd bit line GBL_o is not, the even select transistor SEL_e and the bit line select transistor BLS are turned on, and the odd select transistor SEL_o is turned off. When the odd bit line GBL_o is selected but the even bit line GBL_e is not, the odd select transistor SEL_o and the bit line select transistor BLS are turned on, and the even select transistor SEL_e is turned off. By doing so, one sensing circuit 20 is shared by two 2 bit lines, i.e., the bit lines GBL_e and GBL_o.
When the even bit line GBL_e is selected but the odd bit line GBL_o is not in a read operation, the even bias select transistor YSEL_e is turned off, the odd bias select transistor YSEL_o is turned on, and the odd bit line GBL_o is provided with a ground potential from the virtual potential VIR. Otherwise, when the even bit line GBL_e is not selected but the odd bit line GBL_o is, the even bias select transistor YSEL_e is turned on, the odd bias select transistor YSEL_o is turned off, and the even bit line GBL_e is provided with the ground potential from the virtual potential VIR. By providing the odd bit line with the ground potential when reading the even bit line and providing the even bit line with the ground potential when reading the odd bit line in this way, a bit line shielding effect may be provided to mitigate the noise occurring due to the capacitive coupling between the neighboring bit lines, as described in Japan Patent Publication No. Hei 11-176177.
The sensing circuit 20 illustrated in FIG. 1 is a so-called voltage-type sensing circuit, in which the pre-charge potential is provided to the even bit line GBL_e or the odd bit line GBL_o by the pre-charge transistor BLPRE. Then, the sensing circuit 20 discharges the bit line corresponding to the storage state of the selected memory cell and detects the discharging state at the sensing node SN. However, when a decrease of the bit line linewidth results in increase of the resistance of the bit lines and an increase of the number of the memory cells constituting the NAND string results in an increase of the capacitance between the bit lines, the time constant of the voltage-type sensing circuit is increased and the time for charging/discharging the bit lines is longer, so that the time for reading the data is prolonged. Thus, the voltage-type sensing circuit is no longer applicable to a highly integrated flash memory.
In light of the foregoing, currently used sensing circuits utilize current sensing instead. A current-type sensing circuit detects the cell current of a memory cell corresponding to the storage state through the bit line. Compared with the voltage-type, the current-type sensing circuit is capable of achieving high-speed sensing. The current-type sensing circuit may utilize, for example, a cascode circuit performing current-voltage conversion, or the like.
However, the conventional current-type sensing circuit has the following issues. In a flash memory, electrons are accumulated in the floating gate at programming to positively shift the threshold voltage of the memory cell, and the electrons are ejected from the floating gate at erasure to negatively shift the threshold voltage of the memory cell. However, in the programming or erasure, the threshold voltage of the memory cell has to be controlled within the distribution range of the “0” or “1” storage state, or within the distribution range of the “00”, “01”, “10” or “11” storage state when the memory cell stores multi-bit data. In order to accurately control the threshold voltage of the memory cell, an incremental step pulse erase (ISPE) mode is adopted, where an initiate erase pulse Vers0 is applied to the memory cells in a selected block, and when the erasure is determined to be unsuccessful by erase verification, an erase pulse Vers1 higher than the erase pulse Vers0 by an increment is applied, and the voltage of the erase pulse is gradually increased until the erasure of all memory cells in the block is determined to be successful.
Due to factors such as the size or shape of each memory cell varying with the variation of manufacturing process parameters and deterioration of the tunnel oxide layer resulted from a large number of program/erase cycles, each memory cell differs from one another in being more easily or uneasily erased. In details, some memory cells have high conductance that allows the currents to flow more easily, while some memory cells have low conductance that the currents are less likely to flow. Since the erase verification does not determine the erase states of the memory cells one by one but determines whether the erasure of the entire block is successful with each bit line as a unit, when a bit line is simultaneously connected with memory cells having high conductance and memory cells having low conductance, the memory cells having low conductance become the base for determining whether the erasure is successful, such that the memory cells having high conductance would be over-erased. Therefore, when reading data, the over-erased memory cells have relatively large currents, therefore increasing the power-consumption. In the meantime, the sensing circuit also has to provide a large current, which limits the minimization of the sensing circuit.